• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    improved power cell bypass method and apparatus for multi-level inverter multi-level inverters, power cells and bypass methods are presented in which a power cell switching circuit is selectively switched off from the power cell output , and a bypass that is closed to connect first and second cell output terminals to selectively bypass a power stage of a multi-level inverter, with an optional ac input switch to selectively disconnect the ac input from the switching circuit squid during deviation.
    公开号:BR102014006315A2
    申请号:R102014006315-3
    申请日:2014-03-17
    公开日:2020-05-26
    发明作者:Lixiang Wei；Yuan Xiao；Haihui Lu；Douglas B. Weber
    申请人:Rockwell Automation Technologies, Inc；
    IPC主号:
    专利说明:

    IMPROVED POWER CELL DIVERSION METHOD AND DEVICE FOR MULTIPLE LEVEL INVERTER
    TECHNICAL FIELD
    [001] The present disclosure is directed to a technical field of power conversion, and, more particularly, to a method and apparatus for deviating the power cell for multi-level inverters.
    FUNDAMENTALS
    [002] Multi-level inverters are sometimes used in motor drives and other power conversion applications to generate and supply high voltage drive signals for an engine or other load in high power applications. One form of multi-level inverter is a cascade H-Bridge (CHB) inverter architecture, which employs several power stages connected in series as H-Bridge inverters to drive each motor winding phase. Each H-Bridge is powered by a separate DC source and is triggered by switching signals to generate positive or negative output voltage, with the series combination of H-Bridge multiple stages providing multi-level inverter output capability to drive a load. Device degradation within a particular power stage, however, can inhibit the ability to provide a desired output voltage for a load particularly since the stages are connected in series with each other. Thus, it is desirable to provide the possibility to bypass a particular degraded power stage, for example, to continue operation of a multi-level inverter at reduced output capacity and / or bypass one or more
    2/23 healthy power stages to balance a power converter output to accommodate one or more degraded power stages that have also been bypassed.
    SUMMARY
    [003] Various aspects of the present disclosure are now summarized to facilitate a basic understanding of the disclosure, in which this summary is not an extensive view of the disclosure, and is intended neither to identify certain elements of the disclosure, nor to outline the scope of them. On the contrary, the main objective of this summary is to present several concepts of disclosure in a simplified way before the more detailed description that is presented below. This disclosure provides apparatus and bypass techniques for CHB and other power stages or power cells of a multi-level power converter, in which the H-Bridge or other switching circuit is electrically disconnected from the power stage output, and a bypass switch is closed via the first and second output terminals in order to bypass the stage. Unlike conventional approaches that simply use a bypass switch via the output terminals, the new technique of the present disclosure advantageously prevents or mitigates allowing an engine or other output load to remain electrically connected with a failed cell.
    [004] A power conversion system is provided, which includes multiple power stages connected in series, including individually a switching circuit, a pair of output control switches coupled between the switching circuit and the power stage output ,
    3/23 as well as a bypass switch connected via the outlet. The controller selectively bypasses at least one of the power stages by opening the corresponding output control switches, and closing the bypass switch. In certain embodiments, the output control switches are opened before closing the bypass switch. Certain modalities, in addition, also provide an input switch coupled between an AC input and the power stage switching circuit, where the controller bypasses the power stage by opening the output control switches, closing the bypass switch, and open the input switch.
    [005] A power cell is provided in accordance with other aspects of the present disclosure, which can be used as a power stage in a multi-level inverter circuit. The power cell includes an AC input, a rectifier, a DC link circuit, and a switching circuit with two or more switching devices coupled between the DC link circuit and an output. First and second output control switches are connected between corresponding switching circuit nodes and output terminals, and a bypass switch is coupled via the output. Certain embodiments also include an input switch coupled between the AC input and the switching circuit.
    [006] Methods are revealed to bypass a power stage from a multi-level inverter circuit, including electrically disconnecting a switching circuit from the power stage from a power stage output, and electrically connecting two
    4/23 output terminals from the power stage to each other to bypass the power stage. In certain embodiments, the method also includes electrically disconnecting the switching circuit from an input.
    BRIEF DESCRIPTION OF THE DRAWINGS
    [007] The following description and drawings present certain illustrative implementations of the disclosure in detail, which are indicative of several exemplary ways in which the various principles of disclosure can be realized. The illustrated examples, however, are not exhaustive of the many possible modalities of disclosure. Other objects, advantages and new characteristics of the disclosure will be established in the following detailed description when considered together with the drawings, in which:
    Figure 1 is a schematic diagram illustrating a motor-driven power conversion system based on a three-phase 13-level CHB inverter with a controller providing bypass and switching control signals for the individual power cells;
    Figure 2 is a schematic diagram illustrating an H-bridge power cell or power stage in the power converter of Figure 1 with a three-phase rectifier, a DC link circuit, an inverter, output control switches coupled between the inverter and the load, and a bypass switch to bypass the power cell;
    Figure 3 is a flow chart illustrating an exemplary method for diverting a power cell into a multi-level inverter power conversion system; and
    5/23
    Figure 4 is a schematic diagram illustrating another H-bridge power cell modality with output control switches, a bypass switch, and a multi-phase input switch to bypass the power cell.
    DETAILED DESCRIPTION
    [008] Referring now to the Figures, various modalities or implementations are described below together with the drawings, in which reference numbers are used to refer to equal elements throughout, and in which the various characteristics are not necessarily drawn to scale.
    [009] Figure 1 illustrates an exemplary multi-level inverter motor drive power conversion system that includes a three-phase multi-level inverter 40 with power stages connected in series 100-1, 100-2, 100-3 , 100-4, 100-5, 100-6 for each of the three sections associated with the motor phases U, V and W of a motor load 50. Other modalities are possible in which other forms of load 50 are activated, where the present disclosure is not limited to motor-driven power converters. In certain embodiments, the individual power stages 100 include an H-bridge or inverter switching circuit 140 with switching devices (for example, Q1-Q4 in Figure 2 below), despite any suitable form of switching circuit 140 power be provided in the individual power stages 100 with two or more switches forming a switching circuit to generate a power stage output having one of two or more possible levels according to the signals
    6/23 switching control 222 provided by an inverter control component 220 of a 200 power converter controller.
    [010] The example in Figure 1 is a 13-phase multiphase inverter 40 with six power stages 100 for each of the three motor load phases U, V and W (for example, 100-U1, 100-U2, 100 -U3, 100-U4, 100-U5 and 100-U6 for phase U, 100-V1, 100-V2, 100-V3, 100-V4, 100-V5 and 100-V6 for phase V, and stages 100 -W1, 100-W2, 100-W3, 100-W4, 100-W5, 100-W6 for phase W). The various aspects of the present disclosure can be implemented in association with multiphase multi-level inverter-type power conversion systems having any integer N power stages 100, where N is greater than one. In addition, although the illustrated modalities use cascading H-Bridge 100 stages to form multi-level inverters 40 for each phase of the motor drive system 10, other types and forms of power stages 100 can be used, such as a stage 100 with a switching circuit having more or less than four switching devices, where the broader aspects of the present disclosure are not limited to H-bridge power cells shown in the illustrated modalities. For example, modalities are possible, in which the individual cells can include only two switching devices or any whole number of switches greater than or equal to two.
    [011] As best seen in Figure 1, power converter 10 is supplied with multiphase input power from a phase shift transformer 30
    7/23 having a multiphase primary 32 (a delta configuration in the illustrated mode) receiving three-phase power from an AC 20 power source. Transformer 30 includes 18 three-phase secondary 34, with six sets of three three-phase delta secondary configured 34, with each set being in a different phase relationship. Although primary 32 and secondary 34 are configured as delta windings in the illustrated example, primary windings and / or Y-connected secondary windings or other winding configurations can alternatively be used. In addition, while the transformer has three-phase primary and secondary windings 32, 34, other single- or multi-phase implementations can be used. Although the various secondary 34 in the illustrated modalities are displaced, non-phase displaced modalities are possible.
    [012] Each secondary three-phase 34 in the example in Figure 1 is coupled to supply AC power to drive a three-phase rectifier 120 of a corresponding power stage 100 of the three-phase multi-level inverter 40. Inverter 40 is a 13-level inverter with six cascading H-bridge power steps 100U-1 to 100U-6 having outputs 104U-1 to 104U-6 connected in series with each other (in cascade) between a neutral motor drive point N and a first U winding of a three-phase motor load 50. Likewise, six power stages 100V-1 to 100V-6 provide voltage outputs connected in series 104V-1 to 104V-6 between neutral N and the second winding V, and stages of 100W-1 to 100W-6 power supply 104W-1 series connected voltage outputs
    8/23 to 104W-6 between neutral Neo third winding W motor 50. The controller 200 provides 222U control signals for the power stages 100U-1 to 100U-6 associated with the first motor winding U, and also provides 222V control signals for 10000-6 to 100V-6 power stages and 222W control signals to 100W-6 with 10O power stages. Although the inverter 40 shown in Figure 1 is a multi-phase unit providing output power for phases U, V and W to drive a three-phase motor 50, the concepts of the present disclosure are also applicable for single-phase converters, for example, a converter from three-phase to single-phase matrix receiving a three-phase input from source 20, with a single series connected group of cells 100 providing power to a single-phase motor or other single-phase output load. In addition, other multiphase outputs can be provided having more than three phases.
    [013] With reference also to Figure 2, power cells 100 are provided for use as the power stages of mono or multiphase multi-level inverters 40, with bypass switching devices driven by a bypass component 210 of controller 200. Controller 200 and its components 210, 220 can be implemented using any suitable hardware, software or firmware executed by processor, or combinations thereof, wherein an exemplary embodiment of controller 200 includes one or more processing elements, such as microprocessors, microcontrollers, DSPs, programmable logic, etc., together with electronic memory, program memory and a drive circuit
    9/23 signal conditioning, with the processing element (s) programmed or otherwise configured to generate signals 222 suitable for operating the switching devices of power stages 100. In addition, controller 200 illustrated in certain embodiments implements the drift control component 210 to generate drift control signals 212 for selective drift of one or more of the power stages 100.
    [014] In some implementations, bypass control component 210 provides individual signals or values 212 for individual power cells 100 for direct control over Sla and Slb output control switches (signal (s) 212-1), a bypass switch S2 (signal 212-2) and optionally generates input switching control signal (s) 212-3 to operate an optional S3 input switch (Figure 4 below). In other possible implementations, local switching driver circuits and / or switching logic can be provided within power stages 100 to implement the bypass switching operation as described here based on one or more start actions from the component bypass control 210 or any other control element of, or associated with, the power conversion system 10. For example, a single signal or value can be supplied to an individual power cell 100, and a local logic and / or switching control circuit in cell 100 can initiate the bypass switching operation described in response to receiving such a signal or value.
    [015] Figure 2 illustrates a possible implementation of
    10/23 an H-Bridge 100 power stage. The power stage in Figure 2 is implemented as a power cell 100 that includes an AC input 108 with input terminals 108A, 108B and 108C connectable to receive AC input power. , in the present case three-phase power from an AC source such as a secondary winding 34 of transformer 30 in Figure 1. AC input power is supplied from cell input 108 to a rectifier circuit 120 having built-in rectifier diodes D1 -D6 forming a three-phase rectifier 120 that receives three-phase AC power from the corresponding transformer secondary 34. In this example, a passive rectifier 120 is used, but active rectifier circuits or other forms of rectifiers can be used, whether having a single or multi-phase input. The power cell 100 also includes a DC link circuit 130 and a switching circuit (e.g., inverter bridge-H 14 0) supplying an output voltage V sa i's for a power cell output 104 having first and second output terminals 104A and 104B.
    [016] In the illustrated mode, rectifier 120 supplies DC power through a DC C capacitor connected between the DC link terminals 131 and 132 of the DC link circuit 130. The DC link circuit 130, in turn, provides an input for an H-Bridge inverter 140 formed by four switching devices Q1-Q4 configured in an H bridge circuit. Although the illustrated power stage 100 operates based on the DC power supplied by an internal rectifier circuit 120 driven by an AC input from the transformer secondary
    11/23 corresponding 34, any suitable form of a DC input can be supplied to the power stages 100 according to the present disclosure, and the power stages 100 may, but need not necessarily, include a built-in rectifying circuit 120. In addition , any appropriate switching circuit configuration can be used on switching circuits 140 (eg, inverter) of individual stages 100 having at least two switching devices Q configured to selectively supply voltage at stage output 104 of at least two distinct levels . In addition, any suitable type of Q switching devices can be used in power stages 100, including without limitation semiconductor based switches such as isolated gate bipolar transistors (IGBTs), silicon controlled rectifiers (SCRs), shutdown thyristors ports (GTOs), integrated port switched thyristors (IGCTs), etc.
    [017] The four-switched H-Bridge implementation illustrated (Figure 2) advantageously allows the generation of selective switching control signal by controller 200 to provide at least two different voltage levels at output 104 in a controlled manner. For example, a voltage is supplied at output terminals 104A and 104B of a positive DC level substantially equal to the DC bus voltage through the DC link capacitor C (for example, + VDC) when switching devices QI and Q4 are connected (conductive), while the other devices Q2 and Q3 are turned off (non-conductive). On the other hand, a negative output is provided when Q2 and Q3 are turned on while QI and Q4 are turned off (for example, -VDC). Per
    Therefore, the exemplary H-bridge power stage 100 advantageously allows the selection of two different output voltages, and the cascade configuration of six such stages (for example, Figure 1) allows selective switching control signal generation. by the inverter control component 220 to implement 13 different voltage levels for application to the corresponding motor phase U, V or W. It is noted that other possible switching circuits can be used to implement a selectable two, three, or K output levels for individual stages 100, where K is any positive integer greater than 1. Any appropriate logic or circuitry in controller 200 can be used to provide inverter switching control signals 222 at a given power stage 100, where the Controller 200 may also include signal level amplification and / or driver circuits (not shown) to provide appropriate drive voltage and / or sufficient current levels to selectively drive switching devices Q1-Q4, for example, as comparators, carrier wave generators or digital logic and signal drivers.
    [018] For bypass operation, power cell 100 in Figure 2 includes a pair of output control switches Sla and Slb coupled between switching circuit 140 and output 104. In particular, the first output control switch Sla is coupled between a first switching circuit node 141 and a first output terminal 104Ά, and the second output control switch Slb is coupled between a second switching circuit node 142 and the second output terminal 104B. The switches
    13/23 SI output controls are individually operative in a first state to allow current flow between switching circuit 140 and output 104, and in a second state to prevent current from flowing between switching circuit 140 and output 104 according to one or more output switch control signals 212-1 from bypass control component 210. Although a single output switch control signals 212-1 is shown in the example in Figure 2, control signals 212-1 separate output switches can be used for individual switches S1A and S1B in other implementations, which can, but need not be switched at the same time. Output control switches Sl, in addition, can have any suitable form of single or multiple electrical or electromechanical switching devices, including, without limitation semiconductor based switches, contacts, relays, etc. In addition, the power cell 100 includes a bypass switch S2 connected via output terminals 104 and operative according to a bypass control signal 212-2 from controller 210. The bypass switch S2 is operative in a non-conductive state through which the output voltage of the cell Vsaida is controlled by the operation of switching circuit 140, and a conductive state (for example, closed or conductive) to bypass output 104 of switching circuit 140. The bypass switch 102 can have any suitable form of single or multiple electrical or electromechanical switching device.
    [019] In operation of converter 10, bypass controller 210 selectively diverts cell 100 by positioning
    14/23 the first and second output control switch Sla, Slb in the respective second states via signal (s) 212-1 and by positioning the bypass switch S2 in the conductive state using signal 212-2. Opening the SI output control switches effectively disconnects and isolates output 104 (and therefore motor load 50 (Figure 1)) from inverter switching circuit 140. In addition, closing the bypass switch S2 effectively electrically connects the first and second output terminal 104A and 104B to each other in such a way that other power cells 100 in the converter 10 can continue to drive the motor load 50 even when a given power cell 100 has been bypassed. As can be seen in the waveform diagram of Figure 2, in addition, controller 200 is operative in certain implementations to selectively position the output control switches Sla, Slb in the second (open) state at TI time before closing the deviation switch S2 at time T2. In this way, controller 200 effectively isolates output 104 from switching circuit 140 before bypassing output terminals 104A and 104B. Relative timing and sequence of switching operations are not critical in all the modalities of the present description, and can be implemented in different orders in other implementations. The difference in switching times (for example, T2-T1) for the illustrated modes and switching sequences, on the other hand, can be of any suitable length of time controlled by the bypass component 210, for example, based on the value of DC C link capacitance or other considerations such as the operation of
    15/23 potentially degraded devices within the power cell 100 and / or the need to quickly bypass the power cell 100. In certain embodiments, in addition, controller 210 can selectively adjust the bypass switching control timing according to one or more conditions in the power converter 10.
    [020] Figure 3 illustrates a power stage bypass method 300 to bypass a power stage of a multi-level inverter circuit 40, such as power cell 100 in Figure 2 or Figure 4. In certain embodiments, controller 200 includes at least one processor programmed to perform process 300 such as by a bypass control component 210 to provide signals 212 to select one of the power cells 100, along with other features set forth herein (for example, providing signals switching control unit 222 via inverter control component 220) in accordance with computer executable instructions from a non-transitory computer-readable medium, such as a computer memory, a memory within a converter converter control system power (eg controller 200), a CD-ROM, floppy disk, flash drive, database, server, computer, etc., which has instructions executable by computer to perform the controller processes and functionality described here. As long as the exemplary method 300 is represented and described in the form of a series of actions or events, it will be appreciated that the various methods of disclosure are not limited by the illustrated order of such actions or events except where specifically stated herein. In this
    16/23 respect, except when specifically provided below, some actions or events may occur differently and / or concurrently with other actions or events than those illustrated and described here, and not all illustrated steps may be necessary to implement a process or method in accordance with this disclosure. The illustrated methods can be implemented in hardware, software running on the processor, or combinations thereof, in order to provide the concepts of power stage deviation revealed here.
    [021] The bypass operation can be initiated according to any appropriate input signal received by controller 200 in certain implementations. For example, the power conversion controller 200 can detect one or more of the operating conditions of the power converter 10 indicating possible degradation of one or more power stages 100, and can initiate deviation of one or more selected cells 100 in response. In other possible implementations, controller 200 may receive a signal or message from an external device (not shown) and initiate deviation accordingly.
    [022] Bypass operation begins in process 300 by opening the output control switches (SI in Figure 2) between the inverter switching circuit 140 and the output terminals of the power cell 104A and 104B at 302 to effectively electrically disconnect and isolate switching circuit 140 from output 104. In certain embodiments, one or more input switches (for example, S3 in Figure 4 below) are opened at 304 to prevent current flow between AC input (for example,
    17/23 the secondary windings 34 in Figure 1 above) and the rectifier circuit 120 (Figure 2). At 306, a bypass switch (for example, switch S2 in Figures 2 and 4) is closed in order to bypass the power stage output 104. As discussed above, in certain embodiments, bypass switch S2 is closed at 306 after opening the SI output control switches at 302. In addition, if one or more S3 input control switches are used (Figure 4), these can be opened at 304 in certain modalities after the SI output control switches be opened at 302 and before the bypass switch S2 is closed at 306.
    [023] Reference also to Figure 4, another power cell modality 100 is illustrated, which is generally configured as described above in connection with Figure 2. In addition, the modality of Figure 4 includes an input switch S3 coupled between an AC input 108 and the switching circuit 140 of the power stage 100. The input switch S3, in this case, is a three-phase switching device (three contacts), but separate switches can be used for each input phase, with two contacts or two switches being used for a single-phase AC input, three contacts or three switches being used for a three-phase input, etc. In addition, for modalities including an embedded rectifier circuit 120 as shown in Figure 4, input switch S3 can be located between input 108 and rectifier 120. Input switch S3 is operative in a first state (for example, conductive or ON) to allow current to flow between AC 108 input
    18/23 and switching circuit 140 and in a second state (non-conductive or OFF) to prevent current from flowing between the AC input and switching circuit 140. In this mode, controller 200 bypasses power stage 100 through the positioning of the first and second output control switch Sla, Slb in the respective second states (non-conductive or open), as well as by positioning the bypass switch S2 in the conductive state, and by placing the input switch S3 in the second state (no conductive).
    [024] The provision of the input switch S3 in this embodiment advantageously disconnects the power cell 100 and the output 104 from the AC input source, either from the secondary 34 in Figure 1 or from another associated AC input source. As can be seen in Figure 4, in addition, controller 200 in certain embodiments selectively positions the first and second output control switch Sla, slb in the second state, before positioning the input switch S3 in the second state, and can position the input switch S3 in the second state (for example, at time T3 in Figure 4) before positioning the bypass switch S2 in the conductive state. In these modalities, the timing between signals 212 (for example, T2-T1, T3-T1 and T2-T3) can be defined according to any of the considerations described above and can be selectively adjusted by controller 200 based on one or more power converter conditions. As discussed above, on the other hand, other switching sequences and / or relative timing can be implemented in other modalities, where the broader aspects of the present disclosure are not
    19/23 limited by the illustrated examples.
    [025] By prior art and apparatus, a given cell 100 can be effectively bypassed to allow continued operation of the power conversion system 10 regardless of the failure state of cell 100. For example, if one of the upper switches Ql or Q3 (Figures 2 or 4) must fail in a conductive state, the SI output control switches will open, thus disconnecting the output load 50 (Figure 1) from the upper DC link node 131. Likewise, even if one of the lower switches Q2 or attractive for faults in a conductive state, output 104 is electrically isolated from the lower DC rail 132. Thus, the present disclosure advantageously represents a significant advance over conventional multi-level converter cell bypass techniques and protects the output load 50 regardless of the failure condition of a given power cell 100 while allowing the power cell 100 to be diverted for continuous control operation versor 10.
    [026] The above examples are merely illustrative of the various possible modalities of the various aspects of this disclosure, in which equivalent changes and / or modifications will occur to other experts in the art after reading and understanding this specification and the accompanying drawings. In particular with respect to the various functions performed by the components described above (assemblies, devices, systems, circuits, and the like), the terms (including a reference to a medium) used to describe these components are intended to correspond, otherwise to less than
    20/23 indicated, to any component, such as hardware, software running on the processor, or combinations thereof, that performs the specified function of the described component (ie, that is functionally equivalent), although not structurally equivalent to the described structure that performs the role in illustrated implementations of the disclosure. Furthermore, although a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, that feature can be combined with one or more other features of the other implementations that may be desired and advantageous for any particular or particular application. Furthermore, insofar as the terms including, includes, having, has, with, or its variants are used in the description and / or in the claims, the terms are intended to be inclusive in a similar way to the term comprising.
    21/23
    LIST OF COMPONENTS
    10 power conversion system 100 power stages 100-1, 100-2, 100-3, 100-4,100-5, 100-6 plurality of power stages 100-Ul, 100-U2, 100-U3, 100-U4, 100-U5, 100-U6 power stages for U motor load phase 100-V1, 100-V2, 100-V3, V4-100, 100-V5, 100-V6 power stages for V motor loading phase 100-W1, 100-W2, 100-W3, 100-W4, 100-W5, 100-W6 power stages for motor load phase W 104 exit 104A first output terminal 104B second output terminal 108 AC input 108A, 108B, 108C input terminals 120 iretif ic ^ doi three-phase 130 DC link circuit 131, 132 first and second DC link node 140 switching circuit 141 first knot 142 second node 20 AC power source 200 controller 210, 220 diversion components 212 bypass control signals 212-1 switching signal
    22/23
    exit control 212-2 control signalbypass switching 212-3 control signalsinput switching 222 control signalsswitching 222U provides control signals 222V provides control signals 222W control signals 30 transformerphase shift 300 method 302 disconnect stepe »1 to Έ v Ί to τη to 4vm * —L * * 3 * L- · JL ·« 1> dl L 11 L * tZÍ 304 opening step 306 connect stepelectrically 32 multiphase primary 34 three-phase secondary 40 multi-level inverter circuit 50 engine load Ç link capacitance D1-D6 rectifier diodesembedded N neutral Q1-Q4 switching devices Sla first switch
    23/23
    output control Sib second switchoutput control S2 bypass switch S3 input switch T1, T2, T3 switching times U winding V second winding W third winding
    1/5
    权利要求:
    Claims (10)
    [1]
    1. Power conversion system (10), characterized by the fact that it comprises:
    a plurality of power stages (100-1, 100-2, 100-3, 100-4, 100-5, 100-6) connected in series to form a multi-level inverter circuit (40) for connection at a load (50), the power stages (100) individually comprising:
    a switching circuit (140) including a plurality of switching devices (Q1-Q4) coupled between a DC link circuit (130) and an output (104), the switching circuit (Q1-Q4) operative according to a a plurality of switching control signals (222) to provide an output voltage (V out) having an amplitude of one of at least two discrete levels at the output (104), a first output control switch (Sla) coupled between a first node (141) of the switching circuit (140) and a first output terminal (104A), and a second output control switch (Slb) coupled between a second node (142) of the switching circuit (140) and a second output terminal (104B), the first and second output control switch (Sla, Slb) each being operative in a first state to allow current to flow between the switching circuit (140) and the output (104) and in a second state to prevent current from flowing between the switching circuit (140) and the output (104), and a bypass switch (S2) coupled via the output (104) of the switching circuit (140), the
    [2]
    2/5 bypass switch (S2) operating in a non-conductive state and a conductive state to bypass the output (104) of the switching circuit (140); and a controller (200) operative to selectively bypass at least one power stage (100) by positioning the first and second output control switch (Sla, Slb) in the respective second states and positioning the bypass switch (S2) in the conductive state.
    2. Power conversion system (10), according to claim 1, characterized by the fact that the controller (200) is operative to selectively position the first and second output control switch (Sla, Slb) in the second state before positioning the bypass switch (S2).
    [3]
    3. Power conversion system (10), according to claim 2, characterized by the fact that it also comprises an input switch (S3) coupled between an AC input and the switching circuit (140) of at least one stage power (100), the input switch (S3) being operative in a first state to allow current to flow between the AC input and the switching circuit (140) and a second state to prevent current from flowing between the AC input and the circuit switching (140), where the controller (200) is operative to deflect at least one power stage (100) by positioning the first and second output control switch (Sla, Slb) in the respective second states, by positioning the bypass switch (S2) in the conductive state, and by positioning the input switch (S3) in the second state.
    [4]
    4. Power conversion system (10), according to
    3/5 with claim 3, characterized in that the controller (200) is operative to selectively position the first and second output control switch (Sla, Slb) in the second state before positioning the input switch (S3) in the second state.
    [5]
    5. Power conversion system (10), according to claim 4, characterized by the fact that the controller (200) is operative to position the input switch (S3) in the second state before positioning the bypass switch ( S2) in the conductive state.
    [6]
    6. Power conversion system (10), according to claim 1, characterized by the fact that it also comprises an input switch (S3) coupled between an AC input and the switching circuit (140) of at least one stage power (100), the input switch (S3) being operative in a first state to allow current to flow between the AC input and the switching circuit (140) and a second state to prevent current from flowing between the AC input and the circuit switching (140), where the controller (200) is operative to deflect at least one power stage (100) by positioning the first and second output control switch (Sla, Slb) in the respective second states, by positioning the bypass switch (S2) in the conductive state, and by positioning the input switch (S3) in the second state.
    [7]
    7. Power conversion system (10), according to claim 6, characterized by the fact that the controller (200) is operative to selectively position the first and second output control switch (Sla, Slb) in the second state before positioning the power switch
    4/5 input (S3) in the second state.
    [8]
    8. Power conversion system (10), according to claim 1, characterized by the fact that the switching circuit (140) includes four switching devices (Q1-Q4) connected in an H-bridge configuration between the DC link circuit (130) and output (104), and the controller (200) is operative to supply the switching control signals (222) to the four switching devices (Q1-Q4) of the switching circuit (140) to supply the output voltage (V output ) having an amplitude of one of at least two discrete levels at the output (104).
    [9]
    9. Power cell (100) for use as a power stage in a multi-level inverter circuit (40), the power cell (100) characterized by the fact that it comprises:
    an AC input (108) for receiving AC input power;
    a rectifier (120) coupled with the AC input (108);
    a DC link circuit (130) coupled with the rectifier (120) and including at least one capacitance (C) coupled between first and second DC link node (131, 132);
    a switching circuit (140) including a plurality of switching devices (Q1-Q4) coupled between the DC link circuit (130) and an output (104), the switching circuit (Q1-Q4) operative according to a plurality of switching control signals (222) to provide an output voltage (V output ) having an amplitude of one of at least two discrete levels at the output (104);
    a first output control switch (Sla)
    5/5 coupled between a first node (141) of the switching circuit (140) and a first output terminal (104A), and a second output control switch (Slb) coupled between a second node (142) of the switching circuit switch (140) and a second output terminal (104B), the first and second output control switch (Sla, Slb) each being operative according to at least one output switching control signal (212-1) in a first state to allow current to flow between the switching circuit (140) and the output (104) and a second state to prevent current to flow between the switching circuit (140) and the output (104), and a bypass switch (S2) coupled via the output (104) of the switching circuit (140), the bypass switch (S2) operative according to a bypass switching control signal (212-2) in a non-conductive state and in a conductive state to bypass the output (104) of the switching circuit (140).
    [10]
    10. Method (300) for diverting a power stage (100) from a multi-level inverter circuit (40), method (300) characterized by the fact that it comprises:
    electrically disconnecting (302) a switching circuit (140) from the power stage (100) from an output (104) of the power stage (100); and electrically connect (306) two output terminals (104A, 104B) from the power stage (100) to each other to bypass the power stage (100).
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    同族专利:
    公开号 | 公开日
    EP2782240A3|2014-10-29|
    US20160111967A1|2016-04-21|
    CN104065280A|2014-09-24|
    US9240731B2|2016-01-19|
    CN110061629A|2019-07-26|
    EP2782240A2|2014-09-24|
    MX2014003241A|2015-03-25|
    US9787213B2|2017-10-10|
    US20140268928A1|2014-09-18|
    MX342816B|2016-10-13|
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    法律状态:
    2018-04-03| B12F| Appeal: other appeals|
    2020-03-10| B150| Others concerning applications: publication cancelled|Free format text: ANULADA A PUBLICACAO CODIGO 15.21 NA RPI NO 2455 DE 23/01/2018 POR TER SIDO INDEVIDA. 15.21 ANULADO PARA FINS DE PROSSEGUIMENTO DO FLUXO PROCESSUAL DO PEDIDO, EM ATENDIMENTO AO PARECER RECURSAL QUE REFORMOU A DECISAO EM REFERENCIA. |
    2020-05-26| B03A| Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]|
    2020-06-09| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2020-09-08| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2021-02-02| B06A| Notification to applicant to reply to the report for non-patentability or inadequacy of the application [chapter 6.1 patent gazette]|
    2021-07-13| B11B| Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements|
    优先权:
    申请号 | 申请日 | 专利标题
    US13/845,416|2013-03-18|
    US13/845,416|US9240731B2|2013-03-18|2013-03-18|Power cell bypass method and apparatus for multilevel inverter|
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